A bipolar transistor is formed by fabricating a multilayer structure having a subcollector layer, a collector layer, a base layer and an emitter layer deposited in order and then providing electrodes for the emitter, base and subcollector layers, respectively. While an InP heterojunction bipolar transistor is a fast transistor whose cut-off frequency has been reported to be currently the highest, its fastness depends on increasing the current density by reduction of its size and shortening its transit time. If the emitter width is reduced to excess, however, the parasitic collector capacitance under the base where the base contact is formed becomes not negligible and the transistor contrariwise comes to be slowed down in operating speed.
On the other hand, a silicon bipolar transistor then has an oxide film grown in advance and a contact formed on a polycrystalline extrinsic base layer growing thereon to reduce the parasitic collector capacitance. While the same structure has once been attempted to take in a GaAs heterojunction bipolar transistor, too, it has been the state that the base resistance then cannot be so much reduced by the polycrystalline extrinsic base layer to obtain favorable characteristics.
Patent Reference 1 discloses the structure of GaAs bipolar transistor that the extrinsic base layer is formed of a single crystal and an insulator is provided between the extrinsic base layer and a collector contact layer. FIG. 6 is a cross-sectional view typically illustrating the structure of the conventional bipolar transistor disclosed in Patent Reference 1.
As shown in FIG. 6, the bipolar transistor 50 has a collector contact layer 55 formed on a semiconductor substrate 51 and an insulator layer 59 formed on the collector contact layer 55 wherein the insulator layer 59 is opened in at least two portions. The insulator layer 59 used is lower in dielectric constant than a collector layer 54 and the insulator layer 59 in and above at least one of its opening portions has the collector layer 54, a base layer 53, an emitter layer 52 and an emitter electrode 56 arranged in order, forming a region of intrinsic transistor. The upper face of the base layer 53 is positioned higher than that of the insulator layer 59 and an extrinsic base layer (a region of the base layer other than the intrinsic region) is positioned on the insulator layer 59 and in contact with the adjoining base layer 53. This extrinsic base layer 61 is provided with a base electrode 57 for electrical contact with the base layer 53 and the insulator layer 59 in at least one of its opening portions has a collector electrode 58 in contact with the collector contact layer 55.
Patent Reference 1 mentioned above discloses a process of manufacturing a bipolar transistor 50 which comprises the step of forming a collector contact layer 55 on a semiconductor substrate 51, the step of forming an insulator layer 59 of a selected pattern on the collector contact layer 55, the epitaxial growth step of selectively growing a layer of a collector layer 54 and a base layer 53 in and on the opening portion of the insulator layer 59, the step of epitaxially growing an extrinsic base 61 for connection to a peripheral area of this intrinsic base layer 53 and the step, e.g. of epitaxial growth, of forming an emitter layer 52.
Patent Reference 1: Japanese patent laid open application, JP H11-186279 A